Technical Field
Embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device for generating a clock signal using a delay-locked loop (DLL).
Description of Related Art
In recent years, apparatuses which include semiconductor devices employ a growing number of synchronous semiconductor devices, each of which carries out an operation in synchronism with a clock signal, in order to match operation timings between the semiconductor devices mounted thereon. For example, there is, as one of the synchronous semiconductor devices, a double data rate type synchronous dynamic random access memory (DDR-SDRAM) which is one of semiconductor storage devices used as memories of servers, personal computers, or the like. In the synchronous semiconductor device, a DLL circuit for generating an internal clock signal in synchronism with the external clock signal is used in order to bring an output timing of read data into sync with an external clock signal which is a clock signal of a system. In particular, in the synchronous semiconductor device for simultaneously producing a plurality of pieces of data in parallel, it is necessary to reduce delay time differences between the internal clock signals which are supplied to a plurality of output portions for producing the plurality of pieces of data. JP-A-2012-104197 (which corresponds to US 2012/0124409 A1 and which will later be called “Patent Literature 1”) discloses a clock tree for distributing an internal clock signal generated by a DLL circuit to a plurality of input/output buffers and an output replica. Specifically speaking, the clock tree described in Patent Literature 1 disposes wires for connecting input nodes of the clock tree with the plurality of input/output buffers and the output replica, respectively, so that the respective wires are equal in length. Furthermore, the clock tree is configured to dispose buffers between branch points of the wires, respectively. With the above-mentioned structure in Patent Literature 1, it results in reducing delay differences between a plurality of clock signals supplied to the plurality of input/output buffers and the output replica.
However, the clock tree described in Patent Literature 1 has an increased footprint of the wires for connecting the input nodes of the clock tree with the plurality of input/output buffers and the output replica, respectively. As described above, it is to be wished that the configuration disclosed in Patent Literature 1 is further improved in terms of miniaturization of the semiconductor device.